The present invention relates generally to circuitry enhanced for resistance to single event upset (SEU).
Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost. An FPGA typically includes, an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
A well-studied occurrence in circuitry is called xe2x80x9cSingle Event Upset.xe2x80x9d Single Event Upset or SEU is a change in state of a circuit, conventionally a bit storing circuit such as a dynamic random access memory (DRAM) cell, latch, static random access memory (SRAM) cell and the like, caused by an external energy source, such as alpha particles, cosmic rays, energetic neutrons and the like. The seriousness of SEU is increasing as transistor channel length, oxide thickness, and width continue to decrease. Since the geometries have moved to less than 0.25 microns, the problem has been significant enough that efforts are being made to overcome or decrease the seriousness of SEU events.
In a conventional DRAM or SRAM, an SEU may be addressed with error correction. In fact, error-correcting memory is widely commercially available. However, this is not an efficient option for memory used to configure an FPGA, because configuration memory cells are used to define how the CLBs, IOBs, and interconnect structure are configured. Because an individual memory cell is used for control, conventionally without decoding, if a memory cell changes state owing to an SEU, then a logic function under control of such a memory cell may change.
An approach to handling an SEU condition in an FPGA is triple modular redundancy (TMR), namely, use of three sets of memory cells and configurable logic in place of one, where outcome of at least two of the three sets controls FPGA operation. However, this adds considerable cost.
Others have attempted to increase resiliency to an SEU for a memory cell. Referring to FIG. 1, there is shown a schematic diagram of an SEU hardened memory cell 10 of the prior art. Memory cell 10 is a latch having cross-coupled inverters 12 and 14. Resistors 13 and 15 are coupled to respective outputs of inverters 12 and 14. In order to provide SEU resiliency, resistors 13 and 15 each have a resistance of approximately one mega-ohm. Input voltage, Vin 11, is inverted or complemented by inverter 12 to provide output voltage, Vout 12, which voltage drop is SEU hardened owing to voltage drop across resistor 13, and Vout 12 is inverted by inverter 14 to provide Vin, which voltage drop is SEU hardened owing to voltage drop across resistor 15. Unfortunately, formation of a resistor having a resistance sufficient to harden a latch against an SEU consumes a relatively large amount of area, slows performance, and creates complexity for integration with complementary-metal-oxide semiconductor (CMOS) process. Others have used capacitive loading at an input of an inverter 12 or 14; however, capacitive loading also slows performance of latch 10.
Accordingly, it would be desirable and useful to provide an SEU-resistive memory circuit suitable for integration with a CMOS process. Moreover, it would be desirable and useful to provide an SEU-resistive memory circuit that does not consume as much semiconductor wafer area as other SEU-resistive memory circuits and allows for high speed writing, and high SEU resistance when reading.
According to one embodiment of the invention, resistors between cross-coupled inverters are formed from transistors having a high resistance mode in which resistance is on the order of one to several mega-ohms and a low resistance mode in which resistance is a few hundred ohms. In a method of operating this circuit, the circuit is held in its high-resistance mode when not being written to, which is a great majority of the time, and brought to the low resistance mode only for writing. The circuit thus benefits from the SEU-resistivity most of the time, but the circuit also has high performance during a write operation. Further, the area requirement of a resistive transistor is less than the area requirement of a passive resistor, and thus area requirement of the structure is smaller than the prior art structure of FIG. 1.
In another embodiment, two cross coupled inverters have inductors inserted between them, positioned so that writing to the two inverters does not pass current through the inductors. Thus, a transient upset to one of the inverters is not readily carried to the other inverter (causing the memory cell to flip) because it is slowed by the inductor, but a write signal applied directly to the inverter does cause it to flip, as desired.
In another embodiment, transistors are inserted between the two cross-coupled inverters as discussed above, but have gates that are not controllable, being held in their high resistance mode. This embodiment is smaller and simpler to use, and still benefits from the smaller area of a resistive transistor.
In yet another embodiment, gates of CMOS transistors are held at a constant voltage during operation, but the substrate forming the channel regions is controllable. Thus these transistors operate much like bipolar transistors, and benefit from both variable resistance (SEU-resistivity and high speed) and small area.
In another embodiment, control is provided for both the gate and channel voltages.
In still another embodiment, separate transistors are placed between the output of one inverter and the gates of the PMOS and NMOS transistors of the other inverter and they are separately controllable. Preferably an NMOS transistor is placed in the path to the gate of the NMOS transistor of the inverter and a PMOS transistor is placed in the path to the gate of the PMOS inverter transistor. The NMOS transistor is good at passing a high voltage and thus maintains the NMOS inverter transistor fully on during writing. Likewise, the PMOS transistor is good at passing a low voltage and can maintain the PMOS transistor fully on during writing. More importantly for SEU protection, an NMOS transistor is relatively poor at passing a low voltage, and a PMOS transistor is relatively poor at passing a high voltage, which helps when the driving node is momentarily affected by SEU. This is true because an SEU event hitting a PMOS transistor that has been off will cause that transistor to pull high, momentarily passing an erroneous high to the other inverter. Thus, if an environment into which devices having these circuits is placed causes a particular kind of SEU, separate adjustment of transistors providing resistance to the gates of the PMOS and NMOS transistors in the inverters can be made.